Memory cells in non-volatile and other memories are sometimes arranged in physical structures that are referred to as “memory blocks.” During the device's lifetime, memory blocks that are re-programmed intensively may deteriorate and even become unusable.
Methods for managing the usage of memory blocks are known in the art. For example, U.S. Pat. No. 9,430,322, whose disclosure is incorporated herein by reference, describes a system for improving the management and usage of blocks based on intrinsic endurance, which may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block. This may be accomplished by managing blocks with different intrinsic endurance values internally or by partitioning the blocks with different intrinsic endurance values externally for different usage.
U.S. Pat. No. 9,117,533, whose disclosure is incorporated herein by reference, describes a method carried out in a data storage device that includes a memory and a controller. The method includes updating, in the controller, a value of a particular counter of a set of counters, in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular counter. In response to the value of the particular counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory.